Integrated circuits are often manufactured in and on silicon and other semiconductor wafers. Such integrated circuits include literally millions of metal oxide semiconductor (MOS) field effect transistors, having gate lengths on the order of 0.05 microns. Such MOS transistors may include p-channel MOS (PMOS) transistors, and n-channel MOS (NMOS) transistors, depending on their dopant conductivity types.
Wafers are obtained by drawing an ingot of silicon out of a liquid silicon bath. The ingot is made of mono-crystalline (single-crystal) silicon, and is subsequently sawed into individual wafers. A layer of silicon is then deposited over each wafer. Because the wafer is made of mono-crystalline silicon, the deposition conditions can be controlled so that the layer of silicon deposits “epitaxially” over the wafer. “Epitaxy” refers to the manner in which the silicon layer deposits on the wafer. The layer of silicon has a lattice structure, which further follows the structure of the lattice of the mono-crystalline silicon of the wafer. The layer of silicon is also substantially the same material as the mono-crystalline silicon of the wafer, so that the lattice of the silicon layer also has substantially the same spacing as the spacing of the lattice of the mono-crystalline silicon of the wafer.
A gate dielectric layer, a gate electrode, and spacers are subsequently formed on the layer of silicon. Ions are also implanted into the layer of silicon, which form source and drain regions on opposing sides of the gate electrode. A voltage can be applied over the source and drain regions. Current flows from the source region to the drain region through a channel below the gate dielectric layer when a voltage is applied to the gate electrode.
Recent application of high voltage technologies for LCD (Liquid Crystal Display) driver market demands high voltage (6-40V range) transistors with minimum transistor pitch. Reduction of pitch poses serious concerns on transistor's HCI (hot-carrier injection) lifetime. HCI is a phenomenon by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, or maximum electric field, occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel.
For example in n-channel devices, the electric field at the drain causes channel electrons to gain kinetic energy. Electron-electron scattering randomizes the kinetic energy and the electrons become “hot”. Some of these hot electrons have enough energy to create electron-hole pairs through impact ionization of the silicon atoms. Electrons generated by impact ionization join the flow of channel electrons, while the holes flow into the bulk to produce a substrate current in the device. The substrate current is the first indication of the creation of hot carriers in a device. For p-channel devices, the fundamentals of the process are essentially the same except that the role of holes and electrons are reversed.
HCI occurs when some of the hot carriers are injected into the gate oxide near the drain junction, where they induce damage and become trapped. Traps within the gate oxide generally become electron traps, even if they are initially filled with holes. As a result, there is a negative charge density in the gate oxide. The trapped charge accumulates with time, resulting in positive threshold shifts in both n-channel and p-channel devices. It is known that since hot electrons are more mobile than hot holes, HCI causes a greater threshold skew in n-channel devices than p-channel devices.
Unless modifications are made to the transistor structure, problems of sub-threshold current and threshold shift resulting from SCE (short-channel effects) and HCI will remain. To overcome these problems, alternative drain structures such as double-diffused drains (DDDs) and lightly doped drains (LDDs) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce the maximum electric field. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
There appears to be no way to reduce the size of high voltage semiconductor devices, such as DDD MOS transistors or to reduce substrate current and increase lifetime of the transistors.
Thus, a need still remains for an integrated circuit system to lower costs with lower substrate currents, improved lifetime, reduced thermal cycles, and greater packaging densities, to provide and support systems that are capable of achieving optimal thin, high-density footprint semiconductor systems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.